1. Field of the Invention
This invention relates generally to the circuit architecture of non-volatile memory devices, and more particularly to architecture of the sense amplifier and non-volatile memory cell array of DRAM-like non-volatile memory devices.
2. Description of Related Art
In the semiconductor industry, generally there are two important types of CMOS memories. One type is a volatile memory in which the stored data are not retained when its power supply is removed or shut down. The volatile memories include Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). The other type is a non-volatile memory (NVM) in which the stored data can normally be retained for more than 20 years even after the power supply voltage source is completely disconnected.
Today, there are many different kinds of NVM memories aimed for different applications. For example, the most popular NVM today is NAND flash with a very small cell size of about 4λ2 (λ2 being the smallest area in the design rule for a given semiconductor process) and is generally used to store huge blocks of data necessary for audio and video serial applications. The second popular NVM is NOR flash with one-transistor cell of about 10λ2 and is used to store program codes. The third type of NVM is 2-transistor (2T) floating gate tunneling oxide (FLOTOX) electrically erasable programmable read only memory (EEPROM) with a cell size of about 80λ2. Unlike NAND and NOR flash memories that only allow big-block data alterability, EEPROM can achieve the largest number of program/erase (P/E) cycles. In the current design, the EEPROM is capable of 1 million (1M) P/E cycles when it is operated in units of bytes for small data change applications.
Traditionally, a real byte-alterable operation of FLOTOX-based EEPROM memory array is divided into two steps. The first step is to carry out a Fowler-Nordheim (FN) byte-erase operation and then followed by executing a second step of a FN byte-program operation. Typically, in the traditional FLOTOX-based EEPROM cell, a byte-erase operation is designed to apply a +16.0V to the poly2 gates and 0V to the tunneling channels of the floating-gate transistors in the selected byte of the EEPROM memory array. With the 16.0V voltage across a tunneling oxide layer between the poly1 floating gate and the channel region in a P-substrate, a FN-tunneling effect on the EEPROM cell is induced, thus increasing the threshold voltage (Vt) of each cell to a preferred value of above +4.1V, which is referred to as Vt1 and electrically designed to bias the EEPROM cell in a non-conduction state for storing a binary data of “1” in a byte-read operation. The reason that the threshold voltage increases in each cell of the selected byte after a successful byte-erase operation is because the required number of electrons have been successfully injected into the floating-gate storage layer from the respective channel region due to the occurrence of a FN-tunneling effect.
In contrast, a FN byte-program operation is designed to apply +16.0V to the channel regions along with the floating gates biased at 0V to induce a reverse FN tunneling. How many channels are coupled to the programming voltage of +16.0V depends on the number of cells selected for data change from “1” to “0” during the byte-program operation. In a normal byte-program operation, the number of EEPROM bits selected for a data change varies flexibly from 1 to 8 in a selected byte. A successful byte-program operation decreases the threshold voltages of the selected cells from the high-erased value Vt1 of +4.1V to a lower value below −1.6V, which is referred to as Vt0 and designed to bias the EEPROM cell in a conduction state for storing a binary data of “0”. After performing the successful byte-program operation, the stored electrons in the floating-gate of each selected cell are expelled out from the floating-gate layer to the respective channel region.
A completion of a successful byte-write operation means that the EEPROM cells in a selected byte have gone through both successful byte-erase and byte-program operations regardless of their initial threshold voltages being Vt1 or Vt0. Both byte-erase and byte-program operations employ the low-current FN channel tunneling scheme and are performed in unit of byte, which is why the EEPROM memory is referred to as byte-alterable EEPROM. In real embedded EEPROM applications, page-alterable functions combined with byte-alterable functions have been extensively used to meet the specification of 1M endurance cycles under a wide temperature range from −45° C. to +85° C. of the industrial specification.
As it is well known in the EEPROM art, EEPROM cells have an issue in the closure of the threshold voltage gap (Vt-gap) between the high-erased Vt1 and the low programmed Vt0 after a large number of endurance cycles of operation. The high Vt1 of an erased cell would decline but the low Vt0 of a programmed cell would increase after repeated program and erase cycles under all temperature operation, regardless whether the EEPROM device is of the commercial specification (−30° C. to 75° C.), industrial specification (−40° C. to 85° C.) or military (auto) specification (−50° C. to 125° C.).
The Vt-gap closure issue is getting much more severe when the EEPROM devices are operating in a higher temperature environment. The traditional EEPROM byte-alterable array and sense amplifier design have been proven no longer secure and valid to guarantee normal operation with 1M P/E endurance cycles under such a demanding environment. As a result, in order to meet the requirement of 1M or more P/E endurance cycles in unit of byte for high temperature 125° C. specification, new memory architecture needs to be designed to overcome the issue of Vt-gap closure.
In the prior art, one approach proposed to make EEPROM devices work properly in the 125° C. temperature environment is to use an error correction code (ECC) circuit and an algorithm that adds several syndrome bits to each regular byte with an error-correcting capability for the EEPROM data. But under such a high-temperature operating condition, the added syndrome bits of the ECC circuit itself cannot solve the fundamental Vt-gap closure issue of the EEPROM cells after a large number of endurance cycles because the associated traditional EEPROM sense amplifier cannot work with such a narrowed Vt-gap value. As a result, even with the added ECC circuit in the traditional EEPROM device, the failure rate is still high after a large number of repeated P/E cycles in a high-temperature environment.
The traditional EEPROM design is aimed to meet approximately 1.0V Vt-gap goal in normal temperature specification. Therefore, adding the ECC circuit to the traditional EEPROM cell array without fundamental circuit and array design change, the highly stringent specification requirement in auto-grade or military environments still can not be met. There is a strong need in designing an EEPROM device that can work properly even when the Vt-gap has been narrowed down to a very small value in a high temperature environment